In circuit design, we are generally concerned about signal quality issues, but sometimes we limit our research to signal lines and treat power and ground as ideal situations. Although this approach can simplify the problem, it is no longer feasible in high-speed design. Although the direct result of circuit design is reflected in signal integrity, we cannot ignore power integrity design as a result. Because the integrity of the power supply directly affects the signal integrity of the subsequent PCB board. Power integrity and signal integrity are closely related, and in many cases, PCB sample manufacturers believe that the main cause of signal distortion is the power system. For example, excessive ground rebound noise, inappropriate design of decoupling capacitors, severe circuit impact, poor separation of multiple power sources/ground planes, unreasonable geological design, uneven current, and so on.

　　1) Power distribution system

　　Power integrity design is a very complex task, but in recent years, controlling the impedance between the power supply system (power supply and ground plane) has been a key aspect of the design. In theory, the lower the impedance between power systems, the better. The lower the impedance, the smaller the noise amplitude, and the smaller the voltage loss. In actual design, we can determine the desired target impedance by specifying a larger range of voltage and power supply variations, and then adjust the relevant factors in the circuit to approximate the target impedance of various parts of the power system (frequency dependent).

　　2) Ground rebound

　　When the edge rate of high-speed devices is below 0.5ns, the data exchange rate from the high-capacity data bus is particularly fast. When it generates strong ripples in the power layer that can affect the signal, power instability problems can occur. When the current passing through the ground circuit changes, a voltage is generated due to the circuit inductance. When the rising edge is shortened, the rate of current change increases, and the ground rebound voltage increases. At this point, the ground plane (ground wire) is no longer the ideal zero level, and the power supply is also not the ideal DC potential. When the number of gate circuits that open and close simultaneously increases, the ground rebound becomes more severe. For a 128 bit bus, there may be 50_ 100 I/O lines switch on the same clock edge. At this point, the inductance of the power and ground circuits fed back to the I/O driver that is switched simultaneously must be as low as possible, otherwise, a voltage brush will appear when connected to the same ground. Ground rebound can be seen everywhere, such as on chips, packaging, connectors, or circuit boards, which can lead to power integrity issues.

　　From the perspective of technological development, the rising edge of the device will only decrease, and the width of the bus will only increase. The acceptable way to maintain ground rebound is to reduce the power supply and ground distribution inductance. For chips, it means moving to an array chip, placing as much power and ground as possible, and keeping the wiring to the package as short as possible to reduce inductance. For packaging, it means moving layer packaging to bring the ground plane spacing of the power supply closer, as used in BGA packaging. The PCB prototype manufacturer believes that for connectors, it means using more ground pins or redesigning the connectors to have internal power and ground planes, such as connector based ribbon flexible wires. For circuit boards, it means keeping adjacent power sources and ground as close as possible. Due to the proportional relationship between inductance and length, making the connection between the power supply and ground as short as possible will reduce ground noise.