To exceed the limits of the extreme working conditions listed in the manual. All idle inputs on the device must be connected to VDD or VSS and have good contact. All low impedance devices (such as pulse signal generators, etc.) are connected to CMOS or NMOS integrated circuit inputs

　　All MOS integrated circuits (including P-channel MOS, N-channel MOS, complementary MOS-CMOS integrated circuits) have an insulating gate to prevent voltage breakdown. The thickness of the insulation gate oxide layer in general devices is approximately 25nm, 50nm, and 80nm. In front of the high impedance gate of the integrated circuit, there is a resistor diode network for protection. However, the protection network inside the device is not sufficient to avoid electrostatic damage (ESD) to the device. Experiments have shown that the device will fail during high voltage discharge, and the device may also fail due to the accumulation of multiple lower voltage discharges.

　　There are various forms of electrostatic damage according to the severity of the damage, and the most serious and easily occurring is complete damage to the input or output terminals, resulting in a short circuit or open circuit with the power supply VDD GND, and the device completely loses its original function. The second most serious damage is intermittent failure or performance degradation, which is even more difficult to detect. There are also some electrostatic damages that can increase the leakage current and cause device performance to deteriorate. Due to the inevitable occurrence of high electrostatic discharge caused by short-term operations, such as walking on a waxed floor, it can cause electrostatic high voltage of up to 4KV -15KV, which is related to environmental humidity and surface conditions,