1. Parasitic capacitance

　　The through-hole itself has parasitic capacitance to the ground. If the diameter of the isolation hole on the floor layer of the through-hole is known to be D2, the diameter of the through-hole pad is D1, the thickness of the PCB board is T, and the dielectric constant of the board substrate is ε， The parasitic capacitance of the via is approximately C=1.41 ε TD1/(D2-D1). The main impact of parasitic capacitance on the circuit caused by vias is that it prolongs the rise time of the signal and reduces the speed of the circuit.

　　For example, for a PCB board with a thickness of 50Mil, if a through-hole with an inner diameter of 10Mil and a pad diameter of 20Mil is used, and the distance between the pad and the ground copper area is 32Mil, we can approximately calculate the parasitic capacitance of the through-hole using the above formula as follows: C=1.41 × four point four × zero point zero five zero × 0.020/(0.032-0.020)=0.517pF

　　The variation in rise time caused by this capacitance is:

　　T10-90=2.2C (Z0/2)=2.2 × 0.517x (55/2)=31.28ps

　　From these values, it can be seen that although the effect of the parasitic capacitance caused by a single via on the rise delay is not very obvious, if vias are used multiple times in the wiring for interlayer switching, designers still need to carefully consider it.

　　2. Parasitic inductance

　　In the design of high-speed digital circuits, the parasitic inductance of vias often brings greater harm than the parasitic capacitance, as there are both parasitic capacitors and parasitic inductors in vias. Its parasitic series inductance will weaken the contribution of the bypass capacitor and weaken the filtering effectiveness of the entire power system. We can simply calculate the parasitic inductance of a via approximation using the following formula: L=5.08h [ln (4h/d)+1]

　　Where L refers to the inductance of the through hole, h is the length of the through hole, and d is the diameter of the central drilling hole.

　　From the formula, it can be seen that the diameter of the via has a small impact on the inductance, while the length of the via has the greatest impact on the inductance. Using the above example, the inductance of the via can be calculated as:

　　L=5.08 × 0.050 [ln (4 × 0.050/0.010)+1]=1.015nH

　　If the rise time of the signal is 1ns, then its equivalent impedance size is:

　　XL=π L/T10-90=3.19 Ω

　　This impedance cannot be ignored when there is high-frequency current passing through. It is particularly important to note that the bypass capacitor needs to pass through two vias when connecting the power layer and the ground layer, so the parasitic inductance of the vias will increase exponentially.