Signal integrity refers to the ability of a signal to respond with the correct timing and voltage in a circuit. It is a state in which the signal is undamaged and represents the quality of the signal on the signal line.

　　1 Delay

　　Delay refers to the limited speed at which a signal is transmitted on the wires of a PCB board, and there is a transmission delay between the signal being sent from the sending end to the receiving end. The delay of the signal will have an impact on the timing of the system, and the transmission delay mainly depends on the length of the wire and the dielectric constant of the surrounding medium.

　　In high-speed digital systems, the length of signal transmission lines is the most direct factor affecting the phase difference of clock pulses. Clock pulse phase difference refers to the asynchronous arrival of two clock signals at the receiving end.

　　The phase difference of clock pulses reduces the predictability of signal arrival. If the phase difference of clock pulses is too large, an incorrect signal will be generated at the receiving end, as shown in Figure 1. The transmission line delay has become an important part of the clock pulse cycle.

　　2 Reflection

　　Reflection is the echo on the sub transmission line. When the signal delay time is much greater than the signal transition time, the signal line must be considered as a transmission line. When the characteristic impedance of the transmission line does not match the load impedance, a portion of the signal power (voltage or current) is transmitted to the line and reaches the load, but a portion is reflected.

　　If the load impedance is less than the original impedance, the reflection is negative; On the contrary, reflection is positive. The geometric shape of the wiring, incorrect wire termination, transmission through connectors, and discontinuity in the power plane can all cause such reflections.

　　3 Synchronous switching noise (SSN)

　　When multiple digital signals on the PCB board are synchronously switched (such as the data bus and address bus of the CPU), synchronous switching noise will be generated due to the impedance on the power line and ground wire, and ground plane rebound noise (ground bounce) will also appear on the ground wire.

　　The strength of SSN and ground bombs also depends on the I/O characteristics of the integrated circuit, the impedance of the power and plane layers of the PCB board, and the layout and wiring of high-speed devices on the PCB board.